Astera Labs

Principal Architect

Tel Aviv-Yafo, Tel Aviv District, Israel · Work style not stated

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About the role

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EmployerAstera Labs
LocationTel Aviv-Yafo, Tel Aviv District, Israel
Work styleWork style not stated
Employer posted4 months ago

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.

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This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.

Key Responsibilities

Define and drive system and chip-level architecture for high-speed connectivity products
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems
Analyze system requirements and translate them into scalable and efficient hardware architectures
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering
Define and review micro-architecture specifications and ensure alignment across teams
Contribute to standard-based and custom protocols for next-generation AI infrastructure
Support performance modeling, simulation, and architectural validation
Work closely with customers and partners to understand emerging use cases and requirements
Mentor engineers and help build strong technical leadership within the Israel R&D center

Basic Qualifications

10+ years of experience in semiconductor architecture, ASIC design, or system engineering
Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem
Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond)
Experience designing high-speed, low-latency data paths
Solid understanding of SoC architecture and integration challenges
Experience working across full chip development lifecycle
Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs
Ability to influence and collaborate across multiple engineering domains

Preferred Experience

Experience with CXL, NVLink, UALink, or other advanced interconnect protocols
Background in AI/ML infrastructure, data center systems, or hyperscaler environments
Experience with SerDes-based systems and high-speed PHY integration
Familiarity with networking stacks, switching, or RDMA technologies
Experience with performance modeling tools and architectural simulators
Knowledge of power/performance optimization techniques at system level
Track record of driving architecture from concept to silicon

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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