Principal Engineer, RTL Design

High-Speed Interfaces & Protocols

• Lead integration and implementation of industry-standard interfaces including:

• UCIe
• PCIe
• DDR/LPDDR
• CXL
• Ethernet
• High-speed SerDes

• Drive protocol compliance, performance optimization, and subsystem-level integration.

Compute & AI Subsystems

• Integrate and optimize heterogeneous compute architectures involving:

• Multi-core CPUs
• NPUs
• GPUs
• AI/ML Accelerators

• Drive system-level performance, coherency, memory hierarchy, and scalability considerations.

Functional Safety & Security

• Define and implement hardware architectures supporting Functional Safety requirements (ISO 26262 and related standards).
• Develop safety mechanisms including redundancy, fault detection, fault isolation, and diagnostic coverage.
• Drive hardware security architecture including secure boot, key management, access control, and protection mechanisms.

Low-Power Design & UPF

• Lead SoC low-power architecture and implementation.
• Define and review UPF-based power intent for complex multi-voltage, multi-power-domain designs.
• Drive power-aware RTL integration and verification.
• Implement advanced low-power techniques including:

• Power gating
• Clock gating
• Voltage islands
• Retention strategies
• Dynamic power management

Clock & Reset Architecture

• Define and implement complex SoC clocking and reset architectures.
• Drive clock-domain crossing (CDC) and reset-domain crossing (RDC) methodologies.
• Collaborate with implementation teams for timing closure and clock distribution optimization.

Technical Leadership

• Provide technical leadership and mentoring to RTL and integration engineers.
• Drive design reviews, architecture reviews, and methodology improvements.
• Establish best practices for RTL quality, integration, low-power implementation, and design signoff.
• Influence product roadmap and technology strategy through technical expertise.

• M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience.
• Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture.
• Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems.
• Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis.
• Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks.
• Excellent leadership, communication, and project management skills.
• Experience working with global cross-functional teams.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.