Sr Staff Digital Engineer – Microcontroller (MCU) Systems & Architecture

RTL Implementation & Hand-off: Perform RTL coding (Verilog / SystemVerilog) for SYSSS, CPUSS, Peripheral IPs, IOTOP, and ChipTop. Author and deliver clear implementation instructions to MiddleEnd and BackEnd (Physical Design) teams.

Design Verification & Debugging: Create test plans and execute Unit-Level Verification (UT) and Chip-Level / Top-Level Verification (CT) using UVM and SystemVerilog environments. Lead root-cause debugging across IP, MCU, and SoC levels.

Physical Synthesis & Technology Verification: Run module-level physical synthesis and perform top-level technology checks, including High-Level DRC (HLDRC), Static Timing Analysis checks (STAchk), and Design-for-Testability checks (DFTchk) at SYSSS and ChipTop levels.

Architecture & Subsystem Integration:

Define and integrate MCU subsystems around RISC-V and ARM Cortex-M architectures.

Integrate key peripherals (WDT, INTC, IIC, SPI, ADC, etc.) and handle clock domain crossing (CDC) / asynchronous transfer designs across clock and reset boundaries.

Drive interconnect architecture based on AMBA bus protocols (AHB, APB, AXI).

Technical Expertise & Domain Knowledge

IP / MCU / SoC Debugging: Strong hands-on experience in IP, MCU, and SoC level development with expert-level debugging skills across front-end RTL, simulation, and post-synthesis environments.

Processor Cores & Peripherals: Deep understanding of RISC-V and ARM Cortex-M CPU architectures and common MCU peripherals (e.g., Watchdog Timers [WDT], Interrupt Controllers [INTC], I2C/IIC, SPI, ADC).

Bus Protocols & Interconnects: Thorough technical knowledge of AMBA protocols (AHB, APB, AXI, etc.).

Asynchronous Transfer & CDC: In-depth knowledge of Clock Domain Crossing (CDC) and Asynchronous Transfer Design techniques to prevent metastability in multi-clock MCU systems.

HDL & Programming Languages: High proficiency in industry-standard languages:

Hardware / Verification: Verilog, SVA, SystemVerilog, UVM

Embedded Software / Verification: C, C++

Scripting & Automation: Perl, Python

EDA Toolchains: Hands-on experience with industry-standard Cadence and Synopsys EDA tools, including:

Simulators & Debuggers: Xcellium, VCS, SimVision, Verdi

RTL Lint, CDC & Static Analysis: Spyglass, and related static check tools.

Synthesis and netlist check: Design compiler, Formality, STAcheck (PrimeTime), HLDRC, DFTcheck

Design & Verification Flow: Full-flow experience from PRD specification writing to RTL coding, UT/CT testbench creation, verification checklist, coverage.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.